Therefore, waferlevel packaging technology becomes a key technique to develop, along with waferlevel mems release, as has been demonstrated. Mems device packaging, gold and aluminum diffusion. Advanced packaging techniques like fowlp demand mature lithography solutions for the challenging processes required to manufacture highperformance devices. The principle of the proposed packaging sequence is shown in fig. Wafer level packaging for mems hermetically sealed and reliable packaging solutions based on glasssi materials for systeminpackage sip and mems applications creating a hermetically sealed workspace in which the heart of the application can operate under ideal technological conditions, is an ongoing challenge. Finally, a waferlevel vacuum packaging structure was designed for an mems accelerometer, which achieved hermetic packaging and a metal wire interconnection with a single bonding process, and the performances of the accelerometer were examined. The emphasis will be given to the challenges in reliability and the solutions based on the design. The materials qualified today are based on snag and snagcu. Waferlevel mems packaging via thermally released metalorganic membranes. A wafer level packaging process for mems applications, and a mems package produced thereby, in which a soi wafer is bonded to a mems wafer and the electrical feedthroughs are made through the soi wafer. Evolving packaging solutions and issues the packaging for mems devices is transitioning from quad flat noleads qfn packages to laminate based packages.
It is recognized that a major part of the mems cost is the packaging and testing. Wafer level packaging of compound semiconductors andrew strandjord, thorsten teutsch, axel scheffler, bernd otto, anna paat, oscar alinabon and jing li pac tech usa packaging technologies, inc. Based upon the similar techniques as are used for fabricating device interconnect, nearly all waferlevel packaging processes are based upon multilayer, electroplated metal technology. Clara, ca, usa, an20001memsfirstandepisealprocesses. We have a broad suite of equipment for advanced packaging, including ecd, pvd, etch, cvd, and cmp, that enables our customers to implement any packaging scheme, from flip chip to fanout waferlevel packaging fowlp to throughsilicon via tsv we have established a stateoftheart. Until recently, first level packaging for mems was done using glass frit or anodic bond process. Wafer level chip scale package refers to the technology of packaging an integrated circuit at the wafer level, instead of the traditional process of assembling individual units in packages after dicing th em from a wafer. Fowlp technology, based on wafer molding and fine metal processes. The waferlevel package wlp offers small size and low inductance advantages. After this, the bonded wafer stack and the capping of the hermetically packaged mems devices are still rigid enough to do further. The package concept used is based on a wafer level bonding of a capping silicon substrate with throughsubstrate interconnect to an rfmems wafer. The results in production qualification of these alloys in reliability tests are presented. A highresistivity silicon hrs substrate is used as a starting material.
Waferlevel packaging wlp is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits dice and then packaging them. Sep 04, 2017 wafer level packaging allows integration of wafer fab, packaging, test, and burnin at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to. The capping silicon substrate resistivity, substrate thickness. While waferlevel packaging wlp is not a new technology or process, as with all technologies, it evolves. Packaging alternatives include cavity based packages or hybrid cavity packages with half of the package molded and the other half with a cavity. The encapsulation technique is based on thermal decomposition of a. An10439 waferlevel chipscale package fanin wlp and fanout wlp. As figure 2 shows, a sip can be a combination of several technologies including waferlevel packages, 2. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second soi substrate. Wafer level packaging process for packaging mems or other devices. Waferlevel packaging using localized mass deposition. Therefore, wafer level packaging technology becomes a key technique to develop, along with wafer level mems release, as has been demonstrated. The diffusion requires atomic contact between the surfaces due to the atomic.
This paper proposes an overview of wafer boding processes based on. Waferlevel vacuum packaging of microbolometerbased. Wafer level bonding utilizing metal based technologies are coming to the forefront of manufacturing methods in numerous 3d integration schemes and advanced mems processing. Waferlevel packaging is a key technology to guarantee the mems devices lifetime and reliability, and the proportion of the cost is over 30% in the fabrication of mems devices. Furthermore, wafer level packaging paves the way for true integration of wafer fab, packaging, test, and burnin at wafer level, for the ultimate streamlining of the manufacturing process undergone by a device from silicon start to customer shipment.
Us6660564b2 waferlevel throughwafer packaging process for. Li et al waferlevel parylene packaging with rf electronics for wireless retinal prostheses 737 fig. Waferlevel packaging waferlevel packaging wlp refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. Metal based wafer bonding for wlp has several advantages including enhanced hermeticity and it facilitates vertical integration. Latest metal technologies for 3d integration and mems. Waferlevel chipscale package fanin wlp and fanout wlp. Novel su8 based vacuum waferlevel packaging for mems. Copper to copper bonding of tsvs through silicon vias is used for 3d ic stacking of individual layers as well as in 3d packaging operations. A waferlevel packaging process for mems applications, and a mems package produced thereby, in which a soi wafer is bonded to a mems wafer and the electrical feedthroughs are made through the soi wafer. A reconstituted wafer can be processed in either a 200mm or 300mm round format. Unlike the copper damascene processes where the metal is embedded into a permanent dielectric, wafer level packaging makes use of a temporary and patterned. After completing the packaging steps, the wafers were diced with a diamond saw and characterized using scanning electron microscopy sem, nanoindentation, and tape test for metal adhesion.
Backside lamination is applied to enhance the mechanical strength of wlp body. Continuous improvements and modifications to these wlp. Santa clara, ca, usa abstract the microelectronics industry has implemented a number of different wafer level packaging wlp technologies for. Design, process, and reliability of wafer level packaging. Us6660564b2 waferlevel throughwafer packaging process.
The diffusion requires atomic contact between the surfaces. Waferlevel packaging in conventional packaging, the finished wafer is cut up, or diced, into individual chips, which are then bonded and encapsulated. Reliability challenges and design considerations for wafer. Nsmd nonsolder mask defined padsthe soldermask opening is larger than the metal pads. Interconnection and bonding are two main problems in mems waferlevel. Packaging for mems micro electro mechanical systems, which includes encapsulation and electrical interconnection, is indispensable for practical applications. The lid with the knife edge was then forced down onto the base with the metal layer so that a vacuum joint was formed see figure 1. Bondingbased waferlevel vacuum packaging using atomic. Wafer level packaging of compound semiconductors andrew strandjord, thorsten teutsch, axel scheffler, bernd otto. Whats what in advanced packaging semiconductor engineering.
Generic information of package properties such as moisture sensitivity level msl. In some embodiments, a mems wafer with normal thickness is firstly bonded to a cap wafer of normal thickness, followed by a thinning on the backside of the mems wafer. Waferlevel packaging wlp scope the intent of this chapter is to provide a brief overview of wafer level packaging wlp, including wafer level chip scale packaging wlcsp and fan out packaging, as a background for a roadmap for these technologies going forward. Wafer level packaging wlp, which is now a key technology in introducing a new class of devices such as 3d products and mems etc. Hermeticity and high frequency characteristics of thick gold film feedthrough masaaki moriyama et al3d wafer level packaging technology based on the coplanar au. Batchmodes and lithographical steps, which are inherent in foundry processes, are also implemented in wafer level packaging. The bonding technology is also useful for the integration of mems with heterogeneous elements such as cmos complementary metal oxide semiconductor to obtain adequate performance 3. It has some similarities with either approach, to some extent. The paper covers in more detail how advances in both semiconductor content and power advanced wafer level package design and materials have coenabled significant advances in power device capability during recent years. Waferlevel packaging is somewhere between a foundrybased silicon approach and substratebased approach. Nanium presents wlcsp with three metal layers vila do conde, porto, portugal 27th october 2015 nanium s. The packaging process itself is conducted on this wafer. Wafer level packaging in conventional packaging, the finished wafer is cut up, or diced, into individual chips, which are then bonded and encapsulated. Packagingcompatible wafer level capping of mems devices rajarshi saha, nathan fritz, sue ann bidstrupallen, paul a.
Latest metal technologies for 3d integration and mems wafer. Reduced temperature metal based bonding processes for wafer. It is based on a waferlevel bonding of a capping silicon substrate to an rfmems wafer. The process of packaging a wafer prior to dicing is called wafer level packaging. This process is an extension of the wafer fa b process. Dieattach materials and led functional performance. Balancing device requirements and materials properties. Waferlevel parylene packaging with integrated rf electronics.
Waferlevel parylene packaging with integrated rf electronics for wireless retinal prostheses wen li, member, ieee, damien c. Wafer level packaging for mems micronit microfluidics. Vacuumcontrolled waferlevel packaging for micromechanical devices seok jin kang, young soon moon, won ho son et al. From electrical interconnections to wafer level packaging with special emphasis. Hmic wafer level packaging timothy boles, david hoag, margaret barter, richard giacchino, paul hogan, joel goodrich.
Wafer level packaging of mems and 3d integration with cmos. Trends of power semiconductor wafer level packaging. Humayun, member, ieee, and yuchong tai, fellow, ieee abstractthis paper presents an embedded chip integra. Lowtemperature processing, suitable for the packaging of mems devices that are sensitive to high temperatures. Advanced metal eutectic bonding for high volume mems wlp. Vacuumcontrolled wafer level packaging for micromechanical devices seok jin kang, young soon moon, won ho son et al. Research on waferlevel mems packaging with through. Waferlevel packaging of mems prior to dicing can be classi. In its latest evolution as foundrydriven fowlp, it provides a number of new advantages for the handheldmobile wirelessmultimedia product market segment. We have a broad suite of equipment for advanced packaging, including ecd, pvd, etch, cvd, and cmp, that enables our customers to implement any packaging scheme, from flip chip to fanout wafer level packaging fowlp to throughsilicon via tsv.
A study on wafer level vacuum packaging for mems devices. Waferlevel packaging wlp and its applications application. Another wafer bondingbased approach for sealing of devices with thin. Project description joint fuze technology program jftp sponsored project objective develop wafer level packaging techniques that are applicable to high aspect ratio mems devices wafer bonding for hermetic package sealing through vias for electrical connection to sealed devices. This allows cavity evacuation after bonding and sealing with the chip near ambient temperature. The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. This paper describes a new waferlevel packaging technique in which the vacuum cavity is created using siliconglass bonding and is subsequently sealed using localized polysilicon cvd. Packagingcompatible wafer level capping of mems devices. In this paper, an overview of the state of art wlp packaging technologies will be presented. The company provides waferlevel chip scale packaging wlcsp and was among the first in the world to offer waferlevel fanout wlfo packaging in high volume manufacturing.
Compared with conventional technology based on glass frit bonding, the developed technology is advantageous in terms of smaller width of sealing. Two types of land patterns are used for surfacemount packages figure 3. Waferlevel packaging was then carried out using the ppcposs material system. Wafer level chip scale package wlcsp application note nxp. Waferlevel packaging technology for rf mems sciencedirect. The packaging of the timing module consists in the integration of an asic together with a quartzbased or twinsilicon resonator mems which require to be hermetically sealed under vacuum. Our innovative approach to wafer level manufacturing, known as the flexline tm method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow. School of chemical and biomolecular engineering, georgia institute of technology, atlanta, ga 3033200100, united states. The glass based bonding methods are used in over 80% of. Wafer level packaging wlp is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits dice and then packaging them. Recent citations influence of the sputtering glancing angle. The 0level package or cavity is realized using a flipchip assembly method based. Investigation of ausi eutectic wafer bonding for mems.
Tapeand reel requirements are based on the eia481 standard. Applied materials is the industry leader in wafer level packaging wlp processes. Farrens, metal based wafer level packaging, to be published proc. Applied materials is the industry leader in waferlevel packaging wlp processes. Imaps device packaging conference, scottsdale az, march 12, 20 3. Microbolometer focal plane arrays fpas require an ambient with a total pressure of less than 10 mtorr for optimum sensitivity. Smd soldermask defined padsthe soldermask opening is smaller than the metal pad.
Pdf waferlevel mems packaging via thermally released metal. Different approaches have been investigated by taking advantage of the properties of su8, such as chemical resistance, optical transparence, mechanical reliability and versatility. This work presents a simple and lowcost su8 based wafer level vacuum packaging method which is cmos and mems compatible. However, metal based bonding schemes such as metal eutectics and metal diffusion seals provide increased hermeticity levels and facilitate interwafer and.
Wafer level chip scale packaging wlcsp based on redistribution is the key technology which is evolving to system in package sip and heterogeneous integration hi extended by 3d packaging using through silicon vias tsv. Waferlevel mems packaging via thermally released metalorganic membranes t chan a b c d e unity polymer overcoat metal t c t ch insulator figure 1. Latest metal technologies for 3d integration and mems wafer level. Uses eutectic point in metalsi phase diagrams to form silicides. Waferlevel vacuum packaging of microbolometerbased infrared. Moisture related reliability in electronic packaging. Allegro package designer plus silicon layout option. Wafer level stencil printing is allowing a larger flexibility for the selection of lead free solder alloys. This work main focus is the use of gold thermocompression and goldtin transient liquid phase bonding to achieve a hermetic wafer level packaging. Jul, 2016 enter waferlevel packaging, or wlp, sometimes called bumping after the visual appearance of the final process. A wafer level vacuum packaging process greatly reduces the cost of.
Rodger, member, ieee, ellis meng, senior member, ieee, james d. Reduced temperature metal based bonding processes for. Pabo, viorel dragoi, tian tang, and thorsten matthias 2012 reduced temperature metal based bonding processes for wafer level packaging and 3d integration. Wafer level packaging is somewhere between a foundry based silicon approach and substrate based approach. While wafer level packaging wlp is not a new technology or process, as with all technologies, it evolves. Wafertowafer bonding and packaging bsacberkeley sensor. Batchmodes and lithographical steps, which are inherent in foundry processes, are also implemented in waferlevel packaging.